United States Patent 3,547,716
December 15, 1970

Isolation in Epitaxially Grown Monolithic Devices
David DeWitt
Harlan R. Gates
Alan Platt

Filed September 5, 1968
Image of US PATENT 3,547,716

Abstract of the Disclosure

A technique for producing a monolithic semiconductor structure having device isolation, according to which isolation moats or channels are formed in the monolith so as completely to surround each of the individual device "islands." These channels are isolating by virtue of the fact that they define PN junctions with the device islands and with the remainder of the substrate. The channels are simply formed by discrete diffusions into the monolith so that separately formed regions merge together to produce the desired channels.
Figure descriptions: cover graphic

  • Figure 1 is a cross-sectional view of a portion of a monolithic semiconductor structure in accordance with the present invention and particularly illustrating an isolation channel surrounding a transistor device.
  • Figures 2a through 2e show in cross-section the major steps in the method of the present invention for making the isolated device of figure 1.
  • Figure 3 is a cross-sectional view of an underpass resistor fabricated by following the method of the present invention.

 Citations [54]:
3,260,902 07/1966 Porter 3,312,882 04/1967 Pollock 3,327,182 06/1067 Kisinko 3,335,341 08/1967 Lin 3,341,755 09/1967 Husher et al. 3,370,995 02/1968 Lowery et al. 3,379,584 04/1968 Bean et al.
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