United States Patent 3,909,807
September 30, 1975

Integrated Circuit Memory Cell
Alan William Fulton

Filed September 3, 1974
Image of US PATENT 3,909,807

Abstract of the Disclosure

A cell for an integrated circuit memory is formed of two interconnected identical halves. Each such half is integrally formed without surface metal interconnections. The memory is fabricated from a semiconductor body which comprises an epitaxial layer of one conductivity type overlying a semiconductor substrate of the opposite type. Each half comprises a vertical npn transistor having the collector thereof at the exposed surface of the epitaxial layer and a lateral current source transistor. The collector region of each vertical transistor has two metal contacts, one to form a Schottky diode to couple to a bit line, and one to form an ohmic connection for crosscoupling of the two halves. Power is distributed by a line diffused in the epitaxial layer which line comprises the emitters of the lateral current source transistors and power is returned through word lines which are formed in the substrate of the body prior to growth of the epitaxial layer.
Figure descriptions: cover graphic

  • a schematic diagram of a memory cell.

 Citations [54]:
3,537,078 10/1970 Pomeranz 3,564,300 02/1971 Heule 3,575,741 04/1971 Murphy 3,646,230 02/1972 Lynes 3,655,457 04/1972 Duffy
National Museum of American History
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