United States Patent 4,007,478
February 8, 1977

Field Effect Transistor
Hajime Yagi

Filed October 17, 1973
Image of US PATENT 4,007,478

Abstract of the Disclosure

An insulated gate field effect transistor having a narrow channel made by double diffusion. The double-diffused MIS transistor has a buried layer of high impurity concentration beneath the channel region except the portions of the drain contact region or drain electrode. The buried layer of high impurity concentration is of the same impurity as that of the channel region and is so located that the channel-spreading resistance is drastically reduced while the capacitance between the drain and the channel is maintained as small as possible.
Figure descriptions: cover graphic

  • a sectional view of a double-diffused MIS tetrode of the present invention.

 Citations [54]:
3,445,734 05/1969 Pecoraro et al 3,653,978 04/1972 Robinson et al 3,456,168 07/1969 Tatom 3,685,140 08/1972 Engeler 3,461,360 08/1969 Barson et al 3,711,940 01/1973 Allison et al 3,600,647 08/1971 Gray 3,631,310 12/1971 Das
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