United States Patent 4,030,083
June 14, 1977

Self-Refreshed Capacitor Memory Cell
Harry Joseph Boll

Filed December 18, 1975
Image of US PATENT 4,030,083

Abstract of the Disclosure

This invention involves a memory cell of, for example, the metal-oxide-semiconductor (MOS) capacitor type, which is accessed for reading and writing by means of an access network connected to the memory cell through a gating transistor, and which is provided with an independent refresh network for maintaining the memory state of the cell in the absence of an access writing signal. The refresh network includes a pair of IGFET (Insulated Gate Field-Effect Transistors) transistors connected between the MOS capacitor and an AC refresh line which is completely independent of the electrical access network. Either a "full" or "empty" capacitor memory state, binary digital 1 or 0, respectively, is maintained without the need for interrupting the reading and writing of the MOS capacitor through the gating transistor.
Figure descriptions: cover graphic

  • a schematic circuit diagram of an MOS memory cell with refresh, in accordance with a specific embodiment of the invention.

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National Museum of American History
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