United States Patent 4,054,989
October 25, 1977

High Reliability, Low Leakage, Self-Aligned Silicon Gate FET And Method Of Fabricating Same
Irving T. Ho
Jacob Riseman

Filed November 6, 1975
Image of US PATENT 4,054,989

Abstract of the Disclosure

An improved FET structure and method of making same is disclosed. The gate structure of the FET includes a phospho-silicate glass as the insulator and polysilicon as the gate conductor. A thin layer of silicon nitride is formed over the polysilicon and selectively etched so as to remain only over gate areas and other areas where it is desired to extend the polysilicon as a conductor. The unmasked polysilicon is oxidized to form the thick ocide surface coating. The disclosure also describes the use of oxide rings and epitaxial layers to reduce parasitic effects between adjacent FET devices in an integrated circuit.
Figure descriptions: cover graphic

  • a cross-sectional side view of an FET element during one stage of the preferred method of forming the selfaligned silicon gate FET.

 Citations [54]:
3,751,722 08/1973 Richman 3,761,327 09/1973 Harlow
National Museum of American History
HomeSearchChip TalkChip FunPatentsPeoplePicturesCreditsCopyrightComments