United States Patent 4,072,976
February 7, 1978

Gate Protection Device For MOS Circuits
Eliyahou Harari

Filed December 28, 1976
Image of US PATENT 4,072,976

Abstract of the Disclosure

This specification describes an integrated device for the input protection of MOS circuits. It consists of an MOS capacitor formed by the thinning of a section of the input gate dielectric, SiO2, and the thinning of an adjoining section of the gate metal, Al. An incoming pulse of static charge with high amplitude and short duration will break down the thinned dielectric of the capacitor before breaking down the relatively thick portion of the gate dielectric. Since the metal over the thin dielectric is also relatively thin, it evaporates from the vicinity of the fault by the generated Joule heat immediately following the breakdown. Thus, the breakdown is self healed and can be repeated many times without damaging the circuit.
Figure descriptions: cover graphic

  • illustrates a top view of an MOS structure embodying the present invention.

 Citations [54]:
3,387,286 06/1968 Dennard 3,787,717 01/1974 Fischer 3,403,270 09/1968 Pace et al 3,413,497 11/1968 Atalla 3,423,606 01/1969 Wanlass 3,623,217 11/1971 Kawagoe
National Museum of American History
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