United States Patent 4,134,125
January 9, 1979

Passivation of Metallized Semiconductor Substrates
Arthur C. Adams
Cesar D. Capio
Hyman J. Levinstein
Shyam P. Murarka

Filed July 20, 1977
Image of US PATENT 4,134,125

Abstract of the Disclosure

Disclosed is a method and structure for protecting circuit components from the ambient and in particular for protecting the contact metal from the adverse effects of moisture. A first layer of amorphous silicon is deposited over the circuit including the metal contacts. A second layer which may be silicon nitride or silicon dioxide is then deposited over the amorphous silicon. The amorphous silicon layer reduces cracking in the second layer and prevent cracks in the second layer from propagating to the circuit components.
Figure descriptions: cover graphic

  • a cross-sectional view of a portion of an integrated circuit during one stage of fabrication in accordance with one embodiment of the invention.

 Citations [54]:
3,189,973 06/1965 Edwards et al. 3,271,632 09/1966 Hartmann 3,465,209 09/1969 Denning et al. 3,597,667 08/1971 Horn 3,971,061 07/1976 Matsushita et al. 4,062,707 12/1977 Mochizuki et al.
National Museum of American History
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