Abstract of the Disclosure

A process for fabricating a double layer polycrystalline silicon structure for a metal-oxide-semiconductor (MOS) integrated circuit. The upper polycrystalline silicon layer after being etched to forma predetermined pattern is used as a masking member for etching the lower polycrystalline silicon layer, thereby assuring alignment between the layers. A selective etchant which discriminates between the silicon layers is employed

• illustrates the step in the invented process for the fabrication of a memory device with a source and drain region defined in the substrate.

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