United States Patent 4,142,926
March 6, 1979

Self-Aligning Double Polycrystalline Silicon Etching Process
William L. Morgan

Filed June 12, 1978
Image of US PATENT 4,142,926

Abstract of the Disclosure

A process for fabricating a double layer polycrystalline silicon structure for a metal-oxide-semiconductor (MOS) integrated circuit. The upper polycrystalline silicon layer after being etched to forma predetermined pattern is used as a masking member for etching the lower polycrystalline silicon layer, thereby assuring alignment between the layers. A selective etchant which discriminates between the silicon layers is employed
Figure descriptions: cover graphic

  • illustrates the step in the invented process for the fabrication of a memory device with a source and drain region defined in the substrate.

 Citations [54]:
3,721,593 03/1973 Hays et al 3,767,494 10/1972 Muroaka et al 3,817,799 06/1974 Schuter et al 3,897,282 07/1975 White 3,909,325 09/1975 Church et al 3,940,288 02/1976 Takagi et al 3,996,657 12/1976 Simko et al
National Museum of American History
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