United States Patent 4,144,099
March 13, 1979

High Performance Silicon Wafer And Fabrication Process
Harold D. Edmonds
Gary Markovits

Filed October 31, 1977
Image of US PATENT 4,144,099

Abstract of the Disclosure

Gettered semiconductor wafers for integrated circuit device manufacture are prepared by grinding a layer of damage into the back face of the wafer to a depth of about 8-35 microns, heating the wafer to a temperature of about 800 degrees to 1150 degrees Celsius for about 1 to 3 hours and quickly cooling the wafer to a temperature below about 600 degrees Celsius, and polishing both sides of the wafer to form a polished, substantially damage-free front face and a smooth back face which has a residual layer of crystallographic damage to provide additional gettering during device manufacture
Figure descriptions: cover graphic

  • a plan view illustrating the damage pattern formed on the wafer.

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National Museum of American History
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