United States Patent 4,144,590
March 13, 1979

Intermediate Output Buffer Circuit For Semiconductor Memory Device
Norihisa Kitagawa
Lionel S. White, Jr.

Filed December 29, 1976
Image of US PATENT 4,144,590

Abstract of the Disclosure

A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with sense amplifier circuits at the center of each column and an intermediate output buffer having inputs connected to both sides of the column lines. The intermediate output buffer is a bistable circuit wherein the load transistors have clock voltages applied to their gates after an initial sensing period, so the initial sensing of data on the column lines is done without loads. After this initial period, the load transistors are turned on by booting capacitors. Then, transistors shunting the gates of the load devices to the sense nodes function to turn off the load device on the zero logic level side. The gates of these shunting transistors are each controlled by the voltages on the sense node on the opposite side of the bistable circuit
Figure descriptions: cover graphic

  • an electrical schematic diagram of an array of memory cells for a semiconductor memory device which may utilize the circuit of the invention, along with the intermediate output buffers of the invention.

 Citations [54]:
3,678,473 07/1972 Wahlstrom 3,838,295 09/1974 Lindell 3,983,412 09/1976 Roberts et al 3,992,704 11/1976 Kantz 4,031,522 06/1977 Reed at al 4,039,861 08/1977 Heller et al 4,077,031 02/1978 Kitagawa et al
National Museum of American History
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