United States Patent 4,145,702
March 20, 1979

Electrically Programmable Read-Only-Memory Device
John W. Rau III
Harold H. Muller
Richard K. W. Tam
Louis J. Kabell

Filed July 5, 1977
Image of US PATENT 4,145,702

Abstract of the Disclosure

A matrix of columns and rows of conductors with transistors located at the intersection thereof on a semiconductor chip is formed utilizing the washed emitter process which locates the ohmic contact windows close to the PN junction so that a small size piece of free metal, i.e.., not connected to any other conductor , may be located within a short distance, i.e.., one micron or less, to the PN junction selected to be fused during the programming of a Read Only Memory. The small size of the free metal as near as possible to this PN junction minimizes heat losses, reduces power consumption and reduces programming errors normally incurred in the programming of Read Only Memories
Figure descriptions: cover graphic

  • shows the transistor or back-to-back diodes formed in the accordance with the teachings of this invention in cross-sectional view.

 Citations [54]:
3,641,516 02/1972 Castrucci et al 3,733,690 05/1973 Rizzi 3,742,592 07/1973 Rizzi 3,783,048 01/1974 Sanders 3,848,238 11/1974 Rizzi 3,971,058 07/1976 Fagan
National Museum of American History
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