Abstract of the Disclosure

A matrix of columns and rows of conductors with transistors located at the intersection thereof on a semiconductor chip is formed utilizing the washed emitter process which locates the ohmic contact windows close to the PN junction so that a small size piece of free metal, i.e.., not connected to any other conductor , may be located within a short distance, i.e.., one micron or less, to the PN junction selected to be fused during the programming of a Read Only Memory. The small size of the free metal as near as possible to this PN junction minimizes heat losses, reduces power consumption and reduces programming errors normally incurred in the programming of Read Only Memories

• shows the transistor or back-to-back diodes formed in the accordance with the teachings of this invention in cross-sectional view.

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3,733,690  05/1973  Rizzi
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3,783,048  01/1974  Sanders
3,848,238  11/1974  Rizzi
3,971,058  07/1976  Fagan