Abstract of the Disclosure

A one-transistor memory cell is provided in which the depletion-layer capacitance of an MOS capcitor is increased by locally enhancing the substrate dopant concentration. In preferred embodiments the substrate may also be doped adjacent to the substrate-insulator boundry with ions of appropriate conductivity type to form a diode junction in the substrate. The effective capacitance of the memory cell is therefore the capacitance of the insulator in parallel with substantially increased depletion-layer or diode juncttion capacitance

• a memory cell according to a preferred embodiment of the invention.

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3,740,731  06/1973  Ohwada et al
3,740,732  06/1973  Frandon
4,085,498  04/1978  Rideout