United States Patent 4,164,751
August 14, 1979

High Capacity Dynamic RAM Cell
Aloysious F. Tasch, Jr.

Filed November 10, 1976
Image of US PATENT 4,164,751

Abstract of the Disclosure

Disclosed is a memory system capable of being integrated into a semiconductor substrate and having an array of Hi-C memory cells. The Hi-C cells are selectively addressable by row and column lines. Each cell of the array is comprised of a transistor having a source coupled to a bit line, a gate couple to a word line and a drain coupled to a node N. Node N is coupled in parallel to a dielectric capacitor and to a depletion capacitor. The dielectric capacitor and the depletion capacitor are constructed to have substantially the same charge capacity.
Figure descriptions: cover graphic

  • a greatly enlarged cross-sectional view of a emeory cell whose construction embodies the invention.

 Citations [54]:
3,740,732 06/1973 Frandon 3,852,800 12/1974 Ohwada et al. 3,996,655 12/1976 Cunningham et al. 4,003,036 01/1977 Jenne 4,012,757 03/1977 Koo 4,060,738 11/1977 Tasch, Jr. et al.
National Museum of American History
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