Abstract of the Disclosure

A semiconductor memory device in which a plurality of unit memory cells are formed on a semiconductor substrate; each memory cell comprises a main electrode region provided with either of the source and drain region provided with either of the source and drain sections of an MOS transistor, a gate region and an MOS capacitor region, the main electrode region, gate region, and capacitor region being arranged in the order mentioned; a recess is formed in a semiconductor region including the gate region and part of the MOS capacitor region; the gate region is formed in one selected portion of the recess-defining wall body; and part of the capacitor electrode of the capacitor region extends over another selected portion of the recess-defining wall body.

• a sectional view of the upper part of a unit memory cell according to a first embodiment of this invention which is included in a semiconductor memory device with an electrical insulation layer on the upper part taken off.

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