Abstract of the Disclosure

A merged AND/OR array PLA is disclosed wherein the merger is accomplished by forming the gates of the FET devices in the AND array by means of an upper condu ctor layer and the gates of the FET devices in the OR array, which are connected to the drain of the devices in the AND array, by means of lower level conductor layer, so that the devices are contiguous. The PLA structure uses a polysilico n layer for interconnection between AND array FET drains and OR array FET gates, with the AND array FETS and OR array FETs being intermixed in a single array. The OR array outputs are oriented vertically, alternating between the AND produc t terms and ground diffusions. All PLA outputs are oriented vertically within t he same array. Orienting the polycrystalline silicon line parallel to the input line and orienting the axes of the centroids for the AND FETs and the OR FETs parallel to the input line allows a retention of the high density for the array by permitting the placement of output latches on the top and bottom edges of the array and the placement of the input driver/decoder circuits on the lateral edges of the array so that the close pitch of the array can be maintained. Several alternate device structures and their methods of fabrication are disclosed for implementing the merged array PLA. A testing technique and special testing circuitry is disclosed which makes use of the existing bit partitioning input buffer as the source of the existing bit partitioning input buffer as the source of test patterns and the existing output latches as the storage for the test response bits for individually testing both the AND components and the OR components in the merged array PLA

• Figure 1 is a schematic diagram of the testing circuitry to independently input test patterns to either the AND elements or the OR elements of the merged array PLA.
• Figure 2 is a view of the layout for the merged array PLA showing the dual folding capability.

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