Abstract of the Disclosure

A process for forming a CIS (conductor-insulator-semi-conductor) integrated circuit having one or more field-effect memory transistors, and one or more polysilicon resistors and/or polysilicon conductors. The polysilicon components are formed to predetermined sizes, as needed, so that the implant used to establish the memory threshold voltage of the transistor also provides the desired polysilicon resistance value(s). The process may be used to simultaneously form both memory and non-memory transistors

• cross-sectional representations of stages of fabricating an MNOS circuit using the process of the present invention.

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