United States Patent 4,216,489
August 5, 1980

MOS Dynamic Memory In A Diffusion Current Limited Semiconductor Structure
James T. Clemens
Dinesh A. Mehta
James T. Nelson
Charles W. Pearce
Robert C. Sun

Filed January 22, 1979
Image of US PATENT 4,216,489

Abstract of the Disclosure

In a dynamic MOS (Metal Oxide Semiconductor) random access memory, reverse bias leakage currents which deplete stored charges are reduced by minimizing minority carrier generation-type currents. By so minimizing these currents, the leakage currents become dominated by minority carrier diffusion currents. The memory is ideally formed in an upper semiconductor layer (14) of a layered structure (11). The semiconductor layer (14) is grown epitaxially with with a relatively low dopant concentration on a semiconductor substrate (12) with a dopant concentration of the same conductivity type and about three orders of magnitude greater than that of the epitaxially grown layer. The epitaxially grown structure is advantageously suited for the memory circuits in that it may be formed with very low leakage currents. The material further offers by its layered structure a basis for optimizing dynamic memory device characteristics
Figure descriptions: cover graphic

  • Figure 1 is an enlarged view of the epitaxial portion of a semiconductor wafer and depicting various doped regions for forming p-n junctions having low leakage current in accordance with the invention.
  • Figure 2 is a diagram of preferred boron concentrations in the semiconductor material of the wafer of Figure 1.

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