United States Patent 4,221,044
September 9, 1980

Self-Alignment Of Gate Contacts At Local Or Remote Sites
Gordon C. Godejahn, Jr.
Gary L. Heimbigner

Filed June 6, 1978
Image of US PATENT 4,221,044

Abstract of the Disclosure

A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different etch characteristics permits selective oxidation of only desired portions of the structure without need for masking and removal of selected material form desired locations by batch removal processes again without use of masking. There results VLSI circuits having increased density and reliability. The process allows the simultaneous doping of two or more regions resulting in uniformity of device characteristics.
Figure descriptions: cover graphic

  • illustrates a partial plan view of the surface of the semiconductor wafer to be processed in accordance with the present invention. The cross-hatched portions correspond to the various photolithographic masks used in performing the process in accordance with the present invention.

 Citations [54]:
4,124,934 11/1978 DeBrebisson
National Museum of American History
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