United States Patent 4,221,045
September 9, 1980

Self-Aligned Contacts In An Ion Implanted VLSI Circuit
Gordon C. Godejahn, Jr.

Filed June 6, 1978
Image of US PATENT 4,221,045

Abstract of the Disclosure

A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different etch characteristics permits selective oxidation of only desired portions of the structure without need for masking and removal of selected material from desired locations by batch removal processes again without use of masking. There results VSLI circuits having increased density and reliability. The process allows the simultaneous doping of two or more regions resulting in uniformity of device characteristics.
Figure descriptions: cover graphic

  • illustrates a partial plan view of the surface of a semiconductor wafer processed in accordance with the present invention. Additionally illustrated in this drawing figure are the outlines of the protective regions of the various masks used in the process in accordance with the present invention.

 Citations [54]:
4,072,545 02/1978 De La Moneda
National Museum of American History
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