United States Patent 4,222,816
September 16, 1980

Method For Reducing Parasitic Capacitance In Integrated Circuit Structures
Wendell P. Nobel, Jr.
Richard A. Unis

Filed December 26, 1978
Image of US PATENT 4,222,816

Abstract of the Disclosure

A method for reducing parasitic capacitance in semiconductor devices, particularly for the removal of raised portions of conductive layers overlying and capable of being capacitively coupled to other conductors in semiconductor memory integrated circuits. The method provides for the application of masking or photoresist layer over the surface of a substrate containing portions of a conductor to be removed such that the masking layer completely covers the conductor. Next a uniform thickness of the masking layer. Application of the method to a manufacturing process for a dynamic MOSFET memory array is also described in which bit sense line capacitance is substantially reduced.
Figure descriptions: cover graphic

  • a cross-sectional schematic representation of a semiconductor substrate at one stage of processing in accordance with the invention.

 Citations [54]:
3,841,926 10/1974 Garnache et al 3,975,220 08/1976 Quinn et al 3,976,524 08/1976 Feng 4,025,411 05/1977 Hom-Ma 4,045,594 08/1977 Maddocks 4,070,501 01/1978 Corbin et al
National Museum of American History
HomeSearchChip TalkChip FunPatentsPeoplePicturesCreditsCopyrightComments